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for free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. general description the MAX1080/max1081 10-bit analog-to-digital convert- ers (adcs) combine an 8-channel analog-input multiplex- er, high-bandwidth track/hold (t/h), and serial interface with high conversion speed and low power consumption. the MAX1080 operates from a single +4.5v to +5.5v sup- ply; the max1081 operates from a single +2.7v to +3.6v supply. both devices?analog inputs are software config- urable for unipolar/bipolar and single-ended/pseudo-dif- ferential operation. the 4-wire serial interface connects directly to spi/qspi and microwire devices without external logic. a serial strobe output allows direct connection to tms320-family digital signal processors. the MAX1080/ max1081 use an external serial-interface clock to perform successive-approximation analog-to-digital conversions. the devices feature an internal +2.5v reference and a ref- erence-buffer amplifier with a ?.5% voltage-adjustment range. an external reference with a 1v to v dd1 range may also be used. the MAX1080/max1081 provide a hard-wired shdn pin and four software-selectable power modes (normal opera- tion, reduced power (redp), fast power-down (fastpd), and full power-down (fullpd)). these devices can be programmed to automatically shut down at the end of a conversion or to operate with reduced power. when using the power-down modes, accessing the serial interface automatically powers up the devices, and the quick turn- on time allows them to be shut down between all conver- sions. this technique can cut supply current below 100ma at lower sampling rates. the MAX1080/max1081 are available in a 20-pin tssop package. these devices are higher-speed versions of the max148/max149. for more information, refer to the respective data sheet. applications portable data logging data acquisition medical instruments battery-powered instruments pen digitizers process control features 8-channel single-ended or 4-channel pseudo-differential inputs internal multiplexer and track/hold single-supply operation +4.5v to +5.5v (MAX1080) +2.7v to +3.6v (max1081) internal +2.5v reference 400ksps sampling rate (MAX1080) low power: 2.5ma (400ksps) 1.3ma (redp) 0.9ma (fastpd) 2? (fullpd) spi/qspi/microwire/tms320-compatible 4-wire serial interface software-configurable unipolar or bipolar inputs 20-pin tssop package MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference ________________________________________________________________ maxim integrated products 1 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 top view tssop v dd1 v dd2 din sstrb dout gnd refadj ref com ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 MAX1080 max1081 shdn cs sclk 19-1685; rev 0; 5/00 part MAX1080acup MAX1080bcup MAX1080aeup -40? to +85? 0? to +70? 0? to +70? temp. range pin- package 20 tssop 20 tssop 20 tssop typical operating circuit appears at end of data sheet. pin configuration inl (lsb) ?/2 ? ?/2 spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. ordering information continued at end of data sheet. ordering information
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics?ax1080 (v dd1 = v dd2 = +4.5v to +5.5v, com = gnd, f sclk = 6.4mhz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5v at ref, refadj = v dd1 , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd_ to gnd .............................................................. -0.3v to 6v v dd1 to v dd2 ......................................................... -0.3v to 0.3v ch0?h7, com to gnd.......................... -0.3v to (v dd1 + 0.3v) ref, refadj to gnd .............................. -0.3v to (v dd1 + 0.3v) digital inputs to gnd................................................. -0.3v to 6v digital outputs to gnd ............................ -0.3v to (v dd2 + 0.3v) digital output sink current .................................................25ma continuous power dissipation (t a = +70?) 20-pin tssop (derate 7.0mw/? above +70?) ........ 559mw operating temperature ranges max108_ _cup ................................................. 0? to +70? max108_ _eup............................................... -40? to +85? storage temperature range ............................ -60? to +150? lead temperature (soldering, 10s) ................................ +300? MAX1080a sinad > 58db -3db point f in = 200khz, v in = 2.5vp-p f in1 = 99khz, f in2 =102khz MAX1080b no missing codes over temperature up to the 5th harmonic conditions mhz 0.5 6.4 f sclk serial clock frequency ps <50 aperture jitter ns 10 aperture delay ns 468 t acq track/hold acquisition time ? 2.5 t conv conversion time (note 5) khz 350 full-linear bandwidth mhz 6 full-power bandwidth db -78 channel-to-channel crosstalk (note 4) db 76 imd intermodulation distortion db 70 sfdr spurious-free dynamic range db -70 thd total harmonic distortion lsb ?.5 inl relative accuracy (note 2) bits 10 resolution db 60 sinad signal-to-noise plus distortion ratio lsb ?.1 channel-to-channel offset-error matching ppm/? ?.8 gain-error temperature coefficient ?.0 lsb ?.0 dnl differential nonlinearity lsb ?.0 offset error lsb ?.0 gain error (note 3) units min typ max symbol parameter % 40 60 duty cycle dynamic specifications (100khz sine-wave input, 2.5vp-p, 400ksps, 6.4mhz clock, bipolar input mode) dc accuracy (note 1) conversion rate
ma MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference _______________________________________________________________________________________ 3 electrical characteristics?ax1080 (continued) (v dd1 = v dd2 = +4.5v to +5.5v, com = gnd, f sclk = 6.4mhz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5v at ref, refadj = v dd1 , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) conditions units min typ max symbol parameter to power down the internal reference for small adjustments, from 1.22v 0 to 1ma output load on/off leakage current, v ch_ = 0 or v dd1 t a = +25 c bipolar, v com or v ch_ = v ref /2, referenced to com or ch_ unipolar, v com = 0 v/v +2.05 buffer voltage gain v 1.4 v dd1 - 1.0 refadj buffer disable threshold mv ?00 refadj input range v 1.22 refadj output voltage ? 0.01 10 capacitive bypass at refadj ? 4.7 10 capacitive bypass at ref mv/ma 0.1 2.0 load regulation (note 7) ppm/? ?5 tc v ref ref output temperature coefficient ma 30 ref short-circuit current v 2.480 2.500 2.520 v ref ref output voltage pf 18 input capacitance ? ?.001 ? multiplexer leakage current ? ref /2 v v ref v ch_ input voltage range, single ended and differential (note 6) v in = 0 or v dd2 in power-down mode, f sclk = 0 v ref = 2.500v, f sclk = 0 v ref = 2.500v, f sclk = 6.4mhz (note 8) pf c in input capacitance ? ? i in input leakage v 0.2 v hyst input hysteresis v 0.8 v inl input low voltage v 3.0 v inh input high voltage 5 320 ? 200 350 ref input current v 1.0 v dd1 + 50mv ref input voltage range i sink = 5ma v 0.4 v ol output voltage low 15 i source = 1ma v 4 v oh output voltage high cs = 5v ? ?0 i l three-state leakage current cs = 5v pf 15 c out three-state output capacitance analog inputs (ch7?h0, com) external reference (reference buffer disabled, reference applied to ref) internal reference digital inputs (din, sclk, cs , shdn ) digital outputs (dout, sstrb)
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference 4 _______________________________________________________________________________________ v dd1 = v dd2 = 5.5v v dd1 = v dd2 = 5v ?0%, midscale input conditions ma 2.5 4.0 i vdd1+ i vdd2 supply current v 4.5 5.5 v dd1, v dd2 positive supply voltage (note 9) 1.3 2.0 0.9 1.5 ? 210 mv ?.5 ?.0 psr power-supply rejection units min typ max symbol parameter normal operating mode (note 10) reduced-power mode (note 11) fast power-down mode (note 11) full power-down mode (note 11) electrical characteristics?ax1080 (continued) (v dd1 = v dd2 = +4.5v to +5.5v, com = gnd, f sclk = 6.4mhz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5v at ref, refadj = v dd1 , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) electrical characteristics?ax1081 (v dd1 = v dd2 = +2.7v to +3.6v, com = gnd, f sclk = 4.8mhz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5v at ref, refadj = v dd1 , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) max1081a sinad > 58db -3db point f in = 150khz, v in = 2.5vp-p f in1 = 73khz, f in2 = 77khz max1081b no missing codes over temperature up to the 5th harmonic conditions khz 250 full-linear bandwidth mhz 3 full-power bandwidth db -78 channel-to-channel crosstalk (note 4) db 76 imd intermodulation distortion db 70 sfdr spurious-free dynamic range db -70 thd total harmonic distortion lsb ?.5 inl relative accuracy (note 2) bits 10 resolution db 60 sinad signal-to-noise plus distortion ratio lsb ?.2 channel-to-channel offset-error matching ppm/? ?.6 gain-error temperature coefficient ?.0 lsb ?.0 dnl differential nonlinearity lsb ?.0 offset error lsb ?.0 gain error (note 3) units min typ max symbol parameter power supply dc accuracy (note 1) dynamic specifications (75khz sine-wave input, 2.5vp-p, 300ksps, 4.8mhz clock, bipolar input mode)
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference _______________________________________________________________________________________ 5 electrical characteristics?ax1081 (continued) (v dd1 = v dd2 = +2.7v to +3.6v, com = gnd, f sclk = 4.8mhz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5v at ref, refadj = v dd1 , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) normal operating mode normal operating mode normal operating mode conditions mhz 0.5 4.8 f sclk serial clock frequency ps <50 aperture jitter ns 10 aperture delay ns 625 t acq track/hold acquisition time ? 3.3 t conv conversion time (note 5) units min typ max symbol parameter to power down the internal reference for small adjustments, from 1.22v 0 to 0.75ma output load on/off leakage current, v ch_ = 0 or v dd1 t a = +25 c bipolar, v com or v ch_ = v ref /2, referenced to com or ch_ unipolar, v com = 0 v/v 2.05 buffer voltage gain v 1.4 v dd1 - 1 refadj buffer disable threshold mv ?00 refadj input range v 1.22 refadj output voltage ? 0.01 10 capacitive bypass at refadj ? 4.7 10 capacitive bypass at ref mv/ma 0.1 2.0 load regulation (note 7) ppm/? ?5 tc v ref ref output temperature coefficient ma 15 ref short-circuit current v 2.480 2.500 2.520 v ref ref output voltage pf 18 input capacitance ? ?.001 ? multiplexer leakage current ? ref /2 % 40 60 duty cycle v v ref v ch_ input voltage range, single ended and differential (note 6) v in = 0 or v dd2 in power-down mode, f sclk = 0 v ref = 2.500v, f sclk = 0 v ref = 2.500v, f sclk = 4.8mhz (note 8) pf 15 c in input capacitance ? ? i in input leakage v 0.2 v hyst input hysteresis v 0.8 v inl input low voltage v 2.0 v inh input high voltage 5 ref input current 320 ? 200 350 v 1.0 v dd1 + 50mv ref input voltage range v/v +2.05 buffer voltage gain conversion rate analog inputs (ch7?h0, com) internal reference external reference (reference buffer disabled, reference applied to ref) digital inputs (din, sclk, cs , shdn )
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference 6 _______________________________________________________________________________________ v dd1 = v dd2 = 3.6v i source = 0.5ma v dd1 = v dd2 = 2.7v to 3.6v, midscale input conditions ma 2.5 3.5 i vdd1 + i vdd2 supply current v 2.7 3.6 v dd1, v dd2 v v dd2 - 0.5v v oh output voltage high positive supply voltage (note 9) 1.3 2.0 normal operating mode (note 10) reduced-power mode (note 11) 0.9 1.5 fast power-down mode (note 11) full power-down mode (note 11) ? 210 mv ?.5 ?.0 psr power-supply rejection units min typ max symbol parameter i sink = 5ma v 0.4 v ol output voltage low cs = 3v ? ?0 i l three-state leakage current cs = 3v pf 15 c out three-state output capacitance electrical characteristics?ax1081 (continued) (v dd1 = v dd2 = +2.7v to +3.6v, com = gnd, f sclk = 4.8mhz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5v at ref, refadj = v dd1 , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) timing characteristics?ax1080 (figures 1, 2, 6, 7; v dd1 = v dd2 = +4.5v to +5.5v, t a = t min to t max , unless otherwise noted.) c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf conditions ns 100 t csw cs pulse width high ns 65 t ste cs fall to sstrb enable ns 65 t doe cs fall to dout enable ns 10 65 t std cs rise to sstrb disable ns 10 65 t dod cs rise to dout disable ns 80 t stv sclk rise to sstrb valid ns 80 t dov sclk rise to dout valid ns 62 t cl sclk pulse width low ns 62 t ch ns 156 t cp sclk period sclk pulse width high ns 10 20 t sth sclk rise to sstrb hold ns 10 20 t doh sclk rise to dout hold ns 35 t cs1 cs rise to sclk rise ignore ns 35 t cso sclk rise to cs fall ignore ns 35 t ds din to sclk setup ns 0 t dh din to sclk hold ns 35 t css cs fall to sclk rise setup ns 0 t csh sclk rise to cs rise hold units min typ max symbol parameter digital outputs (dout, sstrb) power supply
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference _______________________________________________________________________________________ 7 timing characteristics?ax1081 (figures 1, 2, 6, 7; v dd1 = v dd2 = +2.7v to +3.6v, t a = t min to t max , unless otherwise noted.) c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf conditions ns 100 t csw cs pulse width high ns 85 t ste cs fall to sstrb enable ns 85 t doe cs fall to dout enable ns 13 85 t std cs rise to sstrb disable ns 13 85 t dod cs rise to dout disable ns 100 t stv sclk rise to sstrb valid ns 100 t dov sclk rise to dout valid ns 83 t cl sclk pulse width low ns 83 t ch ns 208 t cp sclk period sclk pulse width high ns 13 20 t sth sclk rise to sstrb hold ns 13 20 t doh sclk rise to dout hold ns 45 t cs1 cs rise to sclk rise ignore ns 45 t cso sclk rise to cs fall ignore ns 45 t ds din to sclk setup ns 0 t dh din to sclk hold ns 45 t css cs fall to sclk rise setup ns 0 t csh sclk rise to cs rise hold units min typ max symbol parameter note 1: tested at v dd1 = v dd2 = v dd(min) , com = gnd, unipolar single-ended input mode. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. note 3: offset nulled. note 4: ground the ?n?channel; sine wave is applied to all ?ff?channels. note 5: conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. note 6: the common-mode range for the analog inputs (ch7?h0 and com) is from gnd to v dd1 . note 7: external load should not change during conversion for specified accuracy. guaranteed specification of 2mv/ma is the result of production test limitations. note 8: adc performance is limited by the converter? noise floor, typically 300?p-p. note 9: electrical characteristics are guaranteed from v dd1(min) = v dd2(min) to v dd1(max) = v dd2(min) . for operations beyond this range, see typical operating characteristics . for guaranteed specifications beyond the limits, contact the factory. note 10: ain= midscale. unipolar mode. MAX1080 tested with 20pf on dout, 20pf on sstrb, and f sclk = 6.4mhz, 0 to 5v. max1081 tested with same loads, f sclk = 4.8mhz, 0 to 3v. note 11: sclk = din = gnd, cs = v dd1 .
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference 8 _______________________________________________________________________________________ typical operating characteristics (MAX1080: v dd1 = v dd2 = 5.0v, f sclk = 6.4mhz; max1081: v dd1 = v dd2 = 3.0v, f sclk = 4.8mhz; c load = 20pf, 4.7? capacitor at ref, 0.01? capacitor at refadj, t a = +25?, unless otherwise noted.) -0.04 -0.08 0 0.08 0.12 0 400 200 600 800 1000 integral nonlinearity vs. digital output code MAX1080/1-01 digital output code inl (lsb) 1200 0.04 -0.05 -0.10 0 0.05 0.10 0 400 200 600 800 1000 differential nonlinearity vs. digital output code MAX1080/1-02 digital output code dnl (lsb) 1200 -0.15 0.15 3.5 3.0 2.5 2.0 1.5 2.5 4.0 3.0 3.5 4.5 5.0 5.5 supply current vs. supply voltage (converting) MAX1080/1-03 supply voltage (v) supply current (ma) 2.0 2.4 2.2 2.8 2.6 3.0 3.2 -40 20 40 -20 0 60 80 100 supply current vs. temperature MAX1080/1-04 temperature ( c) supply current (ma) max1081 MAX1080 normal operation (pd1 = pd0 = 1) redp (pd1 = 1, pd0 = 0) fastpd (pd1 = 0, pd0 = 1) 0 0.5 1.5 1.0 2.0 2.5 2.5 3.5 3.0 4.0 4.5 5.0 5.5 supply current vs. supply voltage (static) MAX1080/1-05 supply voltage (v) supply current (ma) 0 0.5 1.5 1.0 2.0 2.5 -40 0 -20 20 40 60 80 100 supply current vs. temperature (static) MAX1080/1-06 temperature ( c) supply current (ma) MAX1080 (pd1 = 1, pd0 = 1) MAX1080 (pd1 = 1, pd0 = 0) MAX1080 (pd1 = 0, pd0 = 1) max1081 (pd1 = 1, pd0 = 1) max1081 (pd1 = 1, pd0 = 0) max1081 (pd1 = 0, pd0 = 1) 0 0.5 1.5 1.0 2.0 2.5 2.5 3.5 3.0 4.0 4.5 5.0 5.5 shutdown supply current vs. supply voltage MAX1080/1-07 supply voltage (v) supply current ( a) (pd1 = pd0 = 0) 0 0.5 1.5 1.0 2.0 2.5 -40 0 -20 20 40 60 80 100 shutdown supply current vs. temperature MAX1080/1-08 temperature ( c) supply current ( a) max1081 MAX1080 (pd1 = pd0 = 0) 2.4995 2.4997 2.5001 2.4999 2.5003 2.5005 2.5 3.5 3.0 4.0 4.5 5.0 5.5 reference voltage vs. supply voltage MAX1080/1-09 supply voltage (v) reference voltage (v)
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference _______________________________________________________________________________________ 9 2.4988 2.4992 2.4990 2.4996 2.4994 2.5000 2.4998 2.5002 -40 0 20 -20 40 60 80 100 reference voltage vs. temperature MAX1080/1-10 temperature ( c) reference voltage (v) max1081 MAX1080 -0.50 -0.25 0 offset error vs. supply voltage MAX1080/1-11 v dd (v) offset error (lsb) 2.7 3.3 3.0 3.6 -0.50 -0.25 0 -40 10 -15 35 60 85 offset error vs. temperature MAX1080/1-12 temperature ( c) offset error (lsb) -0.75 -0.25 -0.50 0 0.25 2.7 3.3 3.0 3.6 gain error vs. supply voltage MAX1080/1-13 v dd (v) gain error (lsb) -0.50 -0.25 0 max1081 gain error vs. temperature MAX1080/1-14 temperature ( c) gain error (lsb) -40 10 -15 35 60 85 typical operating characteristics (continued) (MAX1080: v dd1 = v dd2 = 5.0v, f sclk = 6.4mhz; max1081: v dd1 = v dd2 = 3.0v, f sclk = 4.8mhz; c load = 20pf, 4.7? capacitor at ref, 0.01? capacitor at refadj, t a = +25?, unless otherwise noted.)
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference 10 ______________________________________________________________________________________ pin description positive supply voltage v dd2 19 input to the reference-buffer amplifier. to disable the reference-buffer amplifier, connect refadj to v dd1 . refadj 12 serial strobe output. sstrb pulses high for one clock period before the msb decision. high imped- ance when cs is high. sstrb 15 serial data input. data is clocked in at sclk? rising edge. din 16 active-low chip select. data will not be clocked into din unless cs is low. when cs is high, dout and sstrb are high impedance. cs 17 serial clock input. clocks data in and out of serial interface and sets the conversion speed. (duty cycle must be 40% to 60%.) sclk 18 reference-buffer output/adc reference input. reference voltage for analog-to-digital conversion. in internal reference mode, the reference buffer provides a 2.500v nominal output, externally adjustable at refadj. in external reference mode, disable the internal buffer by pulling refadj to v dd1 . ref 11 analog and digital ground gnd 13 serial data output. data is clocked out at sclk? rising edge. high impedance when cs is high. dout 14 active-low shutdown input. pulling shdn low shuts down the device, reducing supply current to 2? (typ). shdn 10 ground reference for analog inputs. com sets zero-code voltage in single-ended mode. must be stable to ?.5lsb. com 9 pin sampling analog inputs ch0?h7 1? function name v dd2 6k gnd dout c load 20pf c load 20pf gnd 6k dout a) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol v dd2 6k gnd dout c load 20pf c load 20pf gnd 6k dout a) v oh to high-z b) v ol to high-z figure 1. load circuits for enable time figure 2. load circuits for disable time positive supply voltage v dd1 20
detailed description the MAX1080/max1081 adcs use a successive- approximation conversion technique and input t/h cir- cuitry to convert an analog signal to a 10-bit digital out- put. a flexible serial interface provides easy interface to microprocessors (?s). figure 3 shows a functional dia- gram of the MAX1080/max1081. pseudo-differential input the equivalent circuit of figure 4 shows the MAX1080/ max1081s?input architecture, which is composed of a t/h, input multiplexer, input comparator, switched- capacitor dac, and reference. in single-ended mode, the positive input (in+) is con- nected to the selected input channel and the negative input (in-) is set to com. in differential mode, in+ and in- are selected from the following pairs: ch0/ch1, ch2/ch3, ch4/ch5, and ch6/ch7. configure the channels according to tables 1 and 2. the MAX1080/max1081 input configuration is pseudo- differential because only the signal at in+ is sampled. the return side (in-) is connected to the sampling capacitor while converting and must remain stable within ?.5lsb (?.1lsb for best results) with respect to gnd during a conversion. if a varying signal is applied to the selected in-, its amplitude and frequency must be limited to maintain accuracy. the following equations express the relation- ship between the maximum signal amplitude and its frequency to maintain ?.5lsb accuracy. assuming a sinusoidal signal at in-, the input voltage is determined by: the maximum voltage variation is determined by: a 2.6vp-p, 60hz signal at in- will generate a ?.5lsb error when using a +2.5v reference voltage and a 2.5? conversion time (15 / f sclk ). when a dc refer- ence voltage is used at in-, connect a 0.1? capacitor to gnd to minimize noise at the input. during the acquisition interval, the channel selected as the positive input (in+) charges capacitor c hold . the acquisition interval spans three sclk cycles and ends on the falling sclk edge after the input control word? last bit has been entered. at the end of the acquisition interval, the t/h switch opens, retaining charge on c hold as a sample of the signal at in+. the conver- sion interval begins with the input multiplexer switching c hold from in+ to in-. this unbalances node zero at the comparator? input. the capacitive dac adjusts during the remainder of the conversion cycle to restore node zero to v dd1 /2 within the limits of 10-bit resolu- tion. this action is equivalent to transferring a 12pf ? [(v in + - v in -)] charge from c hold to the binary- weighted capacitive dac, which in turn forms a digital representation of the analog input signal. max d dt v2f 1lsb t v 2t in in conv ref 10 conv ? ? = () = MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference ______________________________________________________________________________________ 11 input shift register control logic int clock output shift register +1.22v reference t/h analog input mux 10 + 2-bit sar adc in dout sstrb v dd1 v dd2 gnd sclk din com refadj ref out ref clock +2.500v 17k 10 11 12 9 14 15 16 17 18 ch6 7 ch7 8 ch4 5 ch5 6 ch1 2 ch2 3 ch3 4 ch0 1 MAX1080 max1081 cs shdn 20 19 13 2.05 a figure 3. functional diagram c hold 12pf r in 800 ? hold input mux c switch * *includes all input parasitics single-ended mode: in+ = ch0?h7, in- = com. pseudo-differential mode: in+ and in- selected from pairs of ch0/ch1, ch2/ch3, ch4/ch5, and ch6/ch7. at the sampling instant, the mux input switches from the selected in+ channel to the selected in- channel. ch0 ref gnd ch1 ch2 ch3 ch4 ch5 ch6 ch7 com zero v dd1 /2 comparator capacitive dac 6pf track figure 4. equivalent input circuit ? in in v sin(2 ft) ?? = ()
table 1. channel selection in single-ended mode (sgl/ dif = 1) sel2 sel1 sel0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 00 0 + 00 1 + 01 0 + 01 1 + 10 0 + 10 1 + 11 0 + 11 1 + table 2. channel selection in pseudo-differential mode (sgl/ dif = 0) sel2 sel1 sel0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 00 0 + 00 1 + 01 0 + 01 1 + 10 0 + 10 1 + 11 0 + 11 1 ? MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference 12 ______________________________________________________________________________________ track/hold the t/h enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. it enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. if the converter is set up for single-ended inputs, in- is connected to com and the converter con- verts the ??input. if the converter is set up for differen- tial inputs, the difference of [( in+) - (in-) ] is converted. at the end of the conversion, the positive input con- nects back to in+ and c hold charges to the input sig- nal. the time required for the t/h to acquire an input signal is a function of how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. the acquisition time, t acq , is the maximum time the device takes to acquire the signal and the minimum time needed for the signal to be acquired. it is calculated by the following equa- tion: t acq = 7 ? (r s + r in ) ? 12pf where r in = 800 ? , r s = the source impedance of the input signal, and t acq is never less than 468ns (MAX1080) or 625ns (max1081). note that source impedances below 4k ? do not significantly affect the adc? ac performance. input bandwidth the adc? input tracking circuitry has a 6mhz (MAX1080) or 3mhz (max1081) small-signal band- width, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using under- sampling techniques. to avoid high-frequency signals being aliased into the frequency band of interest, anti- alias filtering is recommended. analog input protection internal protection diodes, which clamp the analog input to v dd1 and gnd, allow the channel input pins to swing from gnd - 0.3v to v dd1 + 0.3v without damage. however, for accurate conversions near full scale, the inputs must not exceed v dd1 by more than 50mv or be lower than gnd by 50mv. if the analog input exceeds 50mv beyond the sup- plies, do not allow the input current to exceed 2ma.
quick look to quickly evaluate the MAX1080/max1081s analog per- formance, use the circuit of figure 5. the devices require a control byte to be written to din before each conver- sion. connecting din to v dd2 feeds in control bytes of $ff (hex), which trigger single-ended unipolar conver- sions on ch7 without powering down between conver- sions. the sstrb output pulses high for one clock period before the msb of the conversion result is shift- ed out of dout. varying the analog input to ch7 will alter the sequence of bits from dout. a total of 16 clock cycles is required per conversion. all transitions of the sstrb and dout outputs typically occur 20ns after the rising edge of sclk. starting a conversion start a conversion by clocking a control byte into din. with cs low, each rising edge on sclk clocks a bit from din into the MAX1080/max1081s?internal shift register. after cs falls, the first arriving logic ??bit defines the control byte? msb. until this first ?tart?bit arrives, any number of logic ??bits can be clocked into din with no effect. table 3 shows the control-byte format. the MAX1080/max1081 are compatible with spi/ qspi and microwire devices. for spi, select the cor- rect clock polarity and sampling edge in the spi control registers: set cpol = 0 and cpha = 0. microwire, spi, and qspi all transmit a byte and receive a byte at the same time. using the typical operating circuit , the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the adc, and two more 8-bit transfers to clock out the conversion result). see figure 17 for MAX1080/ max1081 qspi connections. simple software interface make sure the cpu? serial interface runs in master mode so the cpu generates the serial clock. choose a clock frequency from 500khz to 6.4mhz (MAX1080) or 4.8mhz (max1081): 1) set up the control byte and call it tb1. tb1 should be of the format: 1xxxxxxx binary, where the xs denote the particular channel, selected conversion mode, and power mode. 2) use a general-purpose i/o line on the cpu to pull cs low. 3) transmit tb1 and simultaneously receive a byte and call it rb1. ignore rb1. 4) transmit a byte of all zeros ($00 hex) and simulta- neously receive byte rb2. 5) transmit a byte of all zeros ($00 hex) and simulta- neously receive byte rb3. 6) pull cs high. MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference ______________________________________________________________________________________ 13 10 f 0.1 f 2.5v v dd1 v dd2 gnd com cs sclk din dout sstrb shdn v dd2 v dd2 0.01 f 0.01 f ch7 refadj ref 4.7 f 0 to +2.500v analog input oscilloscope ch1 ch2 ch3 ch4 *full-scale analog input, conversion result = $3ff (hex) MAX1080 max1081 +3v or +5v external clock sclk sstrb dout* figure 5. quick-look circuit
MAX1080/max1081 figure 6 shows the timing for this sequence. bytes rb2 and rb3 contain the result of the conversion, padded with three leading zeros, two sub-lsb bits, and one trailing zero. the total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. to avoid excessive t/h droop, make sure the total conversion time does not exceed 120?. digital output in unipolar input mode, the output is straight binary (figure 14). for bipolar input mode, the output is two? complement (figure 15). data is clocked out on the ris- ing edge of sclk in msb-first format. serial clock the external clock not only shifts data in and out but also drives the analog-to-digital conversion steps. sstrb pulses high for one clock period after the last bit of the control byte. successive-approximation bit deci- sions are made and appear at dout on each of the next 12 sclk rising edges (figure 6). sstrb and dout go into a high-impedance state when cs goes high; after the next cs falling edge, sstrb outputs a logic low. figure 7 shows the detailed serial-interface timings. the conversion must complete in 120? or less, or droop on the sample-and-hold capacitors may degrade conversion results. data framing the falling edge of cs does not start a conversion. the first logic high clocked into din is interpreted as a start bit and defines the first bit of the control byte. a conversion starts on sclk? falling edge, after the eighth bit of the control byte (the pd0 bit) is clocked into din. the start bit is defined as follows: the first high bit clocked into din with cs low any time the converter is idle, e.g., after v dd1 and v dd2 are applied. or the first high bit clocked into din after bit 4 of a con- version in progress is clocked onto the dout pin. once a start bit has been recognized, the current conver- sion may only be terminated by pulling shdn low. the fastest the MAX1080/max1081 can run with cs held low between conversions is 16 clocks per conversion. figure 8 shows the serial-interface timing necessary to perform a conversion every 16 sclk cycles. if cs is tied low and sclk is continuous, guarantee a start bit by first clocking in 16 zeros. 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference 14 ______________________________________________________________________________________ bit name description 7(msb) start the first logic ??bit after cs goes low defines the beginning of the control byte. 6 sel2 these three bits select which of the eight channels are used for the conversion (tables 1 and 2). 5 sel1 4 sel0 3 uni/bip 1 = unipolar, 0 = bipolar. selects unipolar or bipolar conversion mode. in unipolar mode, an analog input signal from 0 to v ref can be converted; in bipolar mode, the differential signal can range from -v ref /2 to +v ref /2. 2 sgl/dif 1 = single ended, 0 = pseudo-differential. selects single-ended or pseudo-differential conver- sions. in single-ended mode, input signal voltages are referred to com. in pseudo-differential mode, the voltage difference between two channels is measured (tables 1 and 2). 1 pd1 select operating mode. 0(lsb) pd0 pd1 pd0 mode 0 0 full power-down 0 1 fast power-down 1 0 reduced power 1 1 normal operation table 3. control-byte format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (msb) (lsb) start sel2 sel1 sel0 uni/bip sgl/dif pd1 pd0
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference ______________________________________________________________________________________ 15 ___________applications information power-on reset when power is first applied, and if shdn is not pulled low, internal power-on reset circuitry activates the MAX1080/max1081 in normal operating mode, ready to convert with sstrb = low. the MAX1080/max1081 require 10? to reset after the power supplies stabilize; no conversions should be initiated during this time. if cs is low, the first logical 1 on din is interpreted as a start bit. until a conversion takes place, dout shifts out zeros. additionally, wait for the reference to stabilize when using the internal reference. power modes you can save power by placing the converter in one of two low-current operating modes or in full power-down between conversions. select the power mode through bit 1 and bit 0 of the din control byte (tables 3 and 4), or force the converter into hardware shutdown by dri- ving shdn to gnd. the software power-down modes take effect after the conversion is completed; shdn overrides any software power mode and immediately stops any conversion in progress. in software power-down mode, the serial interface remains active while waiting for a new control byte to start conversion and switch to full-power mode. once the conversion is completed, the device goes into the programmed power mode until a new control byte is written. the power-up delay is dependent on the power-down state. software low-power modes will be able to start conversion immediately when running at decreased clock rates (see power-down sequencing ). during power-on reset, when exiting software full power-down mode, or when exiting hardware shutdown, the device goes immediately into full-power mode and is ready to convert after 2? when using an external reference. when using the internal reference, wait for the typical power-up delay from a full power-down (software or hardware) as shown in figure 9. software power-down software power-down is activated using bits pd1 and pd0 of the control byte. when software power-down is asserted, the adc completes the conversion in progress and powers down into the specified low-qui- escent-current state (2?, 0.9ma, or 1.3ma). the first logic 1 on din is interpreted as a start bit and puts the MAX1080/max1081 into its full-power mode. following the start bit, the data input word or control byte also determines the next power-down state. for example, if the din word contains pd1 = 0 and pd0 = 1, a 0.9ma power-down resumes after one conversion. table 4 details the four power modes with the corre- sponding supply current and operating sections. for data rates achievable in software power-down modes, see power-down sequencing . acquisition idle cs sclk din sstrb dout t acq idle conversion rb3 rb2 rb1 sel 2 1 start 4 891216 2024 sel 1 sel 0 uni/ bip sgl/ dif pd1 pd0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 s1 s0 high-z high-z high-z high-z figure 6. single-conversion timing
MAX1080/max1081 hardware power-down pulling shdn low places the converter in hardware power-down. unlike software power-down mode, the conversion is terminated immediately. when returning to normal operation from shdn with an external refer- ence, the MAX1080/max1081 can be considered fully powered up within 2? of actively pulling shdn high. when using the internal reference, the conversion should be initiated only after the reference has settled; its recovery time is dependent on the external bypass capacitors and shutdown duration. power-down sequencing the MAX1080/max1081 automatic power-down modes can save considerable power when operating at less than maximum sample rates. figures 10 and 11 show the average supply current as a function of the sam- pling rate. using full power-down mode full power-down mode (fullpd) achieves the lowest power consumption, up to 1000 conversions per chan- nel per second. figure 10a shows the max1081? power consumption for one- or eight-channel conver- sions utilizing full power-down mode (pd1 = pd0 = 0), with the internal reference and the maximum clock speed. a 0.01? bypass capacitor at refadj forms an rc filter with the internal 17k ? reference resistor, with a 200? time constant. to achieve full 10-bit accuracy, seven time constants or 1.4ms are required after power-up if the bypass capacitor is fully discharged between conversions. waiting this 1.4ms duration in 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference 16 ______________________________________________________________________________________ pd1/pd0 mode converting (ma) after conversion input comparator reference 00 full power-down (fullpd) 2.5 2? off off 01 fast power-down (fastpd) 2.5 0.9ma reduced power on 10 reduced-power mode (redp) 2.5 1.3ma reduced power on 11 normal operating 2.5 2.0ma full power on circuit sections* total supply current table 4. software-controlled power modes *circuit operation between conversions; during conversion all circuits are fully powered up. sclk din dout sstrb t css t ch t cso t cl t dh t ds t doe t ste t csw t cp t csh t cs1 t std t dod t dov t doh t stv t sth cs figure 7. detailed serial-interface timing
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference ______________________________________________________________________________________ 17 sclk 11 1 5 8858 12 12 12 16 16 1 5 16 b4 b9 s0 b4 b9 s0 din sstrb dout cs control byte 0 sss control byte 1 conversion result 1 conversion result 0 control byte 2 s etc. b4 b9 high-z high-z figure 8. continuous 16-clock/conversion timing 0 0.50 0.25 1.00 0.75 1.25 1.50 0.0001 0.01 0.001 0.1 1 10 time in shutdown (s) reference power-up delay (ms) max1081, v dd1 = v dd2 = 3.0v c load = 20pf code = 1010100000 1000 100 10 1 0.1 10 1 100 1k 10k sampling rate (sps) supply current ( a) 8 channels 1 channel 10,000 1000 10 100 1 1 100 10 1k 10k 100k sampling rate (sps) supply current ( a) max1081, v dd1 = v dd2 = 3.0v c load = 20pf code = 1010100000 8 channels 1 channel figure 9. reference power-up delay vs. time in shutdown figure 10a. average supply current vs. sampling rate (sps) using fullpd and internal reference figure 10b. average supply current vs. sampling rate (sps) using fullpd and external reference 2.5 2.0 1.0 1.5 0.5 0 150 250 100 50 200 300 350 sampling rate (sps) supply current (ma) max1081, v dd1 = v dd2 = 3.0v c load = 20pf code = 1010100000 redp fastpd normal operation figure 11. average supply current vs. sampling rate (sps) using fastpd, redp, normal operation, and internal reference
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference 18 ______________________________________________________________________________________ figure 12a. full power-down timing refadj 1.22v 1.22v 0v 2.5ma 2.5ma 1.3ma or 0.9ma din i vdd1 + i vdd2 ref fullpd redp wait 1.4ms (7 x rc) fullpd 1 0 0 11 = rc = 17k ? x 0.01 f dummy conversion 1 1 0 0 0 2.5v 2.5ma 0v 0ma 2.5v 0v figure 12b. fastpd and redp timing 2.5v (always on) 2.5ma 2.5ma din i vdd1 + i vdd2 ref redp redp fastpd 1 1 0 11 1 0 0 1 2.5ma 0.9ma 0.9ma 1.3ma fast power-down (fastpd) or reduced-power (redp) mode instead of in full power-up can further reduce power consumption. this is achieved by using the sequence shown in figure 12a. figure 10b shows the max1081? power consumption for one- or eight-channel conversions utilizing fullpd mode (pd1 = pd0 = 0), an external reference, and the maximum clock speed. one dummy conversion to power up the device is needed, but no wait time is nec- essary to start the second conversion, thereby achiev- ing lower power consumption at up to half the full sampling rate. using fast power-down and reduced power modes fastpd and redp modes achieve the lowest power consumption at speeds close to the maximum sam- pling rate. figure 11 shows the max1081? power con- sumption in fastpd mode (pd1 = 0, pd0 = 1), redp mode (pd1 = 1, pd0 = 0), and for comparison, normal operating mode (pd1 = 1, pd0 = 1). the figure shows power consumption using the specified power-down mode, with the internal reference and conversion con- trolled at the maximum clock speed. the clock speed in fastpd or redp should be limited to 4.8mhz for the MAX1080/max1081. fullpd mode may provide increased power savings in applications where the MAX1080/max1081 are inactive for long periods of time, but intermittent bursts of high-speed conversions are required. figure 12b shows fastpd and redp tim- ing. internal and external references the MAX1080/max1081 can be used with an internal or external reference. an external reference can be connected directly at ref or at the refadj pin. an internal buffer is designed to provide 2.5v at ref for the MAX1080/max1081. the internally trimmed 1.22v reference is buffered with a 2.05v/v gain. internal reference the MAX1080/max1081s?full-scale range with the inter- nal reference is 2.5v with unipolar inputs and ?.25v with bipolar inputs. the internal reference voltage is adjustable by ?00mv with the circuit in figure 13.
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference ______________________________________________________________________________________ 19 external reference an external reference can be placed at the input (refadj) or the output (ref) of the internal reference- buffer amplifier. the refadj input impedance is typi- cally 17k ? . at ref, the dc input resistance is a minimum of 18k ? . during conversion, an external refer- ence at ref must deliver up to 350? dc load current and have 10 ? or less output impedance. if the refer- ence has a higher output impedance or is noisy, bypass it close to the ref pin with a 4.7? capacitor. using the refadj input makes buffering the external reference unnecessary. to use the direct ref input, disable the internal buffer by connecting refadj to v dd1 . transfer function table 5 shows the full-scale voltage ranges for unipolar and bipolar modes. figure 14 depicts the nominal, unipolar input/output (i/o) transfer function, and figure 15 shows the bipolar i/o transfer function. code transi- tions occur halfway between successive-integer lsb values. output coding is binary, with 1lsb = 2.44mv for unipolar and bipolar operation. layout, grounding, and bypassing for best performance, use pc boards; wire-wrap boards are not recommended. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the adc package. figure 16 shows the recommended system ground connections. establish a single-point analog ground (star ground point) at gnd. connect all other analog grounds to the star ground. connect the digital system ground to this ground only at this point. for lowest- noise operation, the ground return to the star ground? power supply should be low impedance and as short as possible. high-frequency noise in the v dd1 power supply may affect the high-speed comparator in the adc. bypass the supply to the star ground with 0.1? and 10? capacitors close to pin 20 of the MAX1080/max1081. +3.3v 510k 24k 100k 0.01 f 12 refadj max1081 figure 13. max1081 reference-adjust circuit output code full-scale transition 11 . . . 111 11 . . . 110 11 . . . 101 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 123 0 (com) fs fs - 3/2lsb fs = v ref + v com zs = v com input voltage (lsb) 1lsb = v ref 1024 figure 14. unipolar transfer function, full scale (fs) = v ref + v com , zero scale (zs) = v com 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 - fs com* input voltage (lsb) output code zs = v com +fs - 1lsb *v com v ref / 2 + v com fs = v ref 2 -fs = + v com -v ref 2 1lsb = v ref 1024 figure 15. bipolar transfer function, full scale (fs) = v ref / 2 + v com , zero scale (zs) = v com
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference 20 ______________________________________________________________________________________ unipolar mode bipolar mode full scale zero scale positive zero negative full scale scale full scale v ref + v com v com v ref / 2 v com -v ref / 2 + v com + v com table 5. full scale and zero scale minimize capacitor lead lengths for best supply-noise rejection. if the power supply is very noisy, a 10 ? resis- tor can be connected as a lowpass filter (figure 16). high-speed digital interfacing with qspi the MAX1080/max1081 can interface with qspi using the circuit in figure 17 (f sclk = 4.0mhz, cpol = 0, cpha = 0). this qspi circuit can be programmed to do a conversion on each of the eight channels. the result is stored in memory without taxing the cpu, since qspi incorporates its own microsequencer. tms320lc3x interface figure 18 shows an application circuit to interface the MAX1080/max1081 to the tms320 in external clock mode. figure 19 shows the timing diagram for this inter- face circuit. use the following steps to initiate a conversion in the MAX1080/max1081 and to read the results: 1) the tms320 should be configured with clkx (trans- mit clock) as an active-high output clock and clkr (tms320 receive clock) as an active-high input clock. clkx and clkr on the tms320 are connect- ed to the MAX1080/max1081? sclk input. 2) the MAX1080/max1081s cs pin is driven low by the tms320? xf_ i/o port to enable data to be clocked into the MAX1080/max1081s din pin. 3) an 8-bit word (1xxxxx11) should be written to the MAX1080/max1081 to initiate a conversion and place the device into normal operating mode. see table 3 to select the proper xxxxx bit values for your specific application. 4) the MAX1080/max1081s sstrb output is moni- tored through the tms320? fsr input. a falling edge on the sstrb output indicates that the con- version is in progress and data is ready to be received from the device. 5) the tms320 reads in 1 data bit on each of the next 16 rising edges of sclk. these data bits represent the 10 + 2-bit conversion result followed by 4 trailing bits, which should be ignored. 6) pull cs high to disable the MAX1080/max1081 until the next conversion is initiated. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values from a straight line on an actual transfer function. this straight line can be a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the static linearity parameters for the MAX1080/max1081 are measured using the best-straight-line fit method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. v dd1 gnd supplies dgnd v dd com gnd v dd1 digital circuitry MAX1080 max1081 *r = 10 ? *optional v dd2 v dd2 figure 16. power-supply grounding connection
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference ______________________________________________________________________________________ 21 aperture width aperture width (t aw ) is the time the t/h circuit requires to disconnect the hold capacitor from the input circuit (for instance, to turn off the sampling bridge and put the t/h unit in hold mode). aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (resid- ual error). the ideal, theoretical minimum analog-to-dig- ital noise is caused only by quantization error and results directly from the adc? resolution (n bits): snr = (6.02 ? n + 1.76)db in reality, there are other noise sources besides quanti- zation noise, including thermal noise, reference noise, clock jitter, etc. therefore, snr is calculated by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamen- tal, the first five harmonics, and the dc offset. 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 MAX1080 max1081 mc683xx ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com shdn v dd2 v dd1 sclk cs din sstrb dout gnd refadj ref v dd1 (power supplies) sck pcs0 mosi miso 0.1 f 10 f (gnd) 4.7 f 0.01 f analog inputs +5v or +3v +5v or +3v figure 17. qspi connections xf clkx clkr dx dr fsr cs sclk din dout sstrb tms320lc3x MAX1080 max1081 figure 18. MAX1080/max1081-to-tms320 serial interface
signal-to-noise plus distortion (sinad) sinad is the ratio of the fundamental input frequency? rms amplitude to rms equivalent of all other adc out- put signals: sinad (db) = 20 ? log (signal rms / noise rms ) effective number of bits (enob) enob indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists only of quantization noise. with an input range equal to the adc? full-scale range, calcu- late enob as follows: enob = (sinad - 1.76) / 6.02 total harmonic distortion (thd) thd is the ratio of the rms sum of the input signal? first five harmonics to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio of the rms amplitude of the funda- mental (maximum signal component) to the rms value of the next-largest distortion component. thd 20 log vvvvv v 2 2 3 2 4 2 4 2 5 2 1 = ++++ ? ? ? ? ? ? MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference 22 ______________________________________________________________________________________ sclk din dout sstrb sel2 start sel1 sel0 pd1 pd0 cs uni/bip sgi/dif b8 s1 msb s0 high impedance high impedance figure 19. MAX1080/max1081-to-tms320 serial interface part temp. range pin- package MAX1080beup max1081aeup max1081beup -40? to +85? -40? to +85? -40? to +85? 20 tssop 20 tssop 20 tssop ? ?/2 inl (lsb) ? max1081acup max1081bcup 0? to +70? 0? to +70? 20 tssop 20 tssop ?/2 ? ordering information (continued) typical operating circuit v dd i/o sck (sk) mosi (so) miso (si) v ss shdn sstrb dout din sclk cs com gnd v dd1 v dd2 ch7 4.7 f 0.1 f ch0 0 to +2.5v analog inputs MAX1080 max1081 cpu +5v or +3v ref 0.01 f refadj v dd2 chip information transistor count: 4286 process: bicmos
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference ______________________________________________________________________________________ 23 ________________________________________________________package information tssop.eps note: the MAX1080/max1081 do not have an exposed die pad.
MAX1080/max1081 300ksps/400ksps, single-supply, low-power, 8-channel, serial 10-bit adcs with internal reference maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2000 maxim integrated products printed usa is a registered trademark of maxim integrated products. notes

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